intoPIX is showcasing the first hardware implementation of the TICO patent-pending lightweight disruptive compression technology running on FPGA hardware.
Without usage of external memory and with a low footprint, TICO FPGA IP-cores provide a visually lossless compression up to 4:1, with a fixed latency of few pixel lines for HD, 4K or 8K. This new image and video compression algorithm is designed to tackle cost and bandwidth challenges.
“Using TICO lightweight compression in FPGA, we are able to achieve higher performance with lower cost infrastructure and systems,” said Gael Rouvroy, intoPIX CTO. “TICO is designed to be a standard for the industry-wide support and can easily map 4K video in 3G-SDI or 10GbE network.”
The ultra-low-footprint encoder and decoder (IPX-TC-UHD4K) will compress any resolutions from HD up 4K resolution at 60fps with lossless visual quality up to 4:1 at a maximum latency of 8 pixel lines. A second lightweight IP-core version will perform mathematically lossless video frame buffer compression-decompression (IPX-TC-MLS).
The NAB demonstrations feature a Xilinx Kintex-7- board and an Altera Cyclone V board running the current FPGA development of the TICO technology.
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